By Luca Fanucci; et al
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Extra resources for An experimental approach to CDMA and interference mitigation : from system architecture to hardware testing through VLSI design
According to the polynomial theory [Pet72], it is possible to select the feedback taps so as to obtain a sequence with the longest possible repetition period L 2m 1 and good correlation properties [Sar80], the so called maximal length or m-sequences. Tables for the configurations of m-sequence generators are easily found in the literature [Dix94], [Pic82]. In an m-sequence the number of logical ‘0’s and ‘1’s is 2m1 1 and 2m1 , respectively [Dix94]. Since in all practical cases we have L 1 the occurrence rate of each symbol is virtually the same within each period, so that such sequences are called balanced.
Application specific processors and configurable solutions improve energy efficiency at the expense of flexibility. The most obvious way of combining flexibility 16 Chapter 1 and cost efficiency is to take the best from different worlds: computationally intensive signal processing tasks are better implemented on DSP (Digital Signal Processor) cores or media processor cores than on a microprocessor core, whilst the opposite is true for control tasks. As shown in Figure 1-13, a typical wireless transceiver combines a data pipe, which gradually transforms the bit serial data stream coming from the Analog to Digital Converter (ADC) into a set of complex data messages, and a protocol stack, that controls the operation of the data pipe.
Baseband equivalent of a DS/SS receiver. After examining the main functions for signal detection, we present some introductory considerations about the practical implementation of a DS/SS receiver. In this respect Figure 2-11 shows a scheme of a DS/SS receiver highlighting also the different signal synchronization functions (carrier frequency/phase and timing) which often represent the real crux of good modem design. We have denoted by 'fˆ , Tˆ , and Wˆ the estimates of the carrier frequency offset, phase offset, and chip timing error, respectively, relevant to the useful signal.
An experimental approach to CDMA and interference mitigation : from system architecture to hardware testing through VLSI design by Luca Fanucci; et al