By Gérard Berry (auth.), Laurence Pierre, Thomas Kropf (eds.)
CHARME’99 is the 10th in a chain of operating meetings dedicated to the dev- opment and use of modern formal strategies and instruments for the layout and veri?cation of and platforms. past meetings were held in Darmstadt (1984), Edinburgh (1985), Grenoble (1986), Glasgow (1988), Leuven (1989), Torino (1991), Arles (1993), Frankfurt (1995) and Montreal (1997). This workshop and convention sequence has been geared up in cooperation with IFIP WG 10. five. it's now the biannual counterpart of FMCAD, which occurs each even-numbered 12 months within the united states. The 1999 occasion happened in undesirable Her- nalb, a inn village situated within the Black wooded area as regards to the town of Karlsruhe. The validation of useful and timing habit is an immense bottleneck in present VLSI layout structures. A predominantly educational quarter of research until eventually many years in the past, formal layout and veri?cation ideas at the moment are migrating into commercial use. the purpose of CHARME’99 is to collect researchers and clients from academia and operating during this lively zone of study. invited talks illustrate significant present traits: the presentation by way of G´erard Berry (Ecole des Mines de Paris, Sophia-Antipolis, France) is anxious with using synchronous languages in circuit layout, and the debate given via Peter Jansen (BMW, Munich, Germany) demonstrates an program of formal tools in an commercial surroundings. this system additionally contains 20 common displays and 12 brief presentations/poster exhibitions which have been chosen from the forty eight submitted papers.
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Extra resources for Correct Hardware Design and Verification Methods: 10th IFIP WG10.5 Advanced Research Working Conference, CHARME’99 BadHerrenalb,Germany,September 27–29, 1999 Proceedings
Term) In this logic, formulas have truth values while terms have values from some arbitrary domain. Memories can be viewed as mappings from domain values, representing addresses, to domain or Boolean values (as determined by the type of the memory), representing data. Terms are formed by applications of uninterpreted function sym- 40 Miroslav N. Velev and Randal E. Bryant bols, and by applications of ITE (for “if-then-else”) and read operators. , ITE(true, x1, x2) yields x1 while ITE(false, x1, x2) yields x2.
Henzinger, Shaz Qadeer, Sriram K. Rajamani, and Serdar Tasiran. An assume-guarantee rule for checking simulation. In Formal Methods in ComputerAided Design, Palo Alto, California, 1998. 32 18. Richard C. Ho, C. Han Yang, Mark A. Horowitz, and David Dill. Architecture validation for processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, 1995. 33 19. Ravi Hosabettu, Mandayam Srivas, and Ganesh Gopalakrishnan. Decomposing the proof of correctness of pipelined microprocessors.
Using this method we construct a formal speciﬁcation for an instruction-set architecture like Intel’s IA-64; and a microarchitectural design that draws inﬂuence from Compaq’s 21264  and Intel’s Merced . We demonstrate how to decompose the microarchitectural correctness proof using the extensions from the speciﬁcation. We then survey related work, and propose several directions for future research. 2 OA-64: An Explicitly Parallel Instruction Set In this section we develop a speciﬁcation of an explicitly parallel instruction-set, called the Oregon Architecture (OA-64), which is based on Intel’s IA-64.
Correct Hardware Design and Verification Methods: 10th IFIP WG10.5 Advanced Research Working Conference, CHARME’99 BadHerrenalb,Germany,September 27–29, 1999 Proceedings by Gérard Berry (auth.), Laurence Pierre, Thomas Kropf (eds.)