By Velijko Milutinovic
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Extra info for Surviving the Design of Microprocessor and Multimicroprocessor Systems: Lessons Learned
Comment: This figure gives only the precise description of the MESI and the SI protocols. Detailed explanations of the rationales behind, and more, are given later on in this book (section on caching in shared memory multiprocessors). Present State Pin Activity M N/A Next State Description M Read hit; data is provided to processor core by cache. No bus cycle is generated. N/A E Read hit; data is provided to processor core by cache. No bus cycle is generated. N/A S Read hit; data is provided to processor core by cache.
The first level caches are on the processor chip; both of them are 2-way set-associative 8KB caches with buffers which handle 4 outstanding misses. The second level cache includes both data and code. It is 4-way set-associative, 256 KB large, and includes 8 ECC (Error Correction Code) bits per 64 data bits. Support for SMP (Shared Memory multiProcessing) and DSM (Distributed Shared Memory) is in the form of the MESI protocol support. Some primitive support for MCS (MultiComputer Systems) and DCS (Distributed Computer Systems) is in the form of two dedicated ports, one for input and one for output.
Comment: Brainiacs use more on-chip resources to enrich the execution unit; consequently, often there is no room for L2 cache on the CPU chip. On the other hand, speedemons are the first ones to include L2 on the same chip as the CPU, which is enabled because the execution unit is simpler. 3. About the Research of the Author and His Associates During the past decade, in the specific area of microprocessor design and architecture, the research and development activities of the author and his associates have concentrated on: design of models of modern 32-bit and 64-bit microprocessors using HDLs (Hardware Description Languages) which are able to run machine/assembly level programs, for the major purpose of: (a) architecture experimentation and (b) silicon compilation.
Surviving the Design of Microprocessor and Multimicroprocessor Systems: Lessons Learned by Velijko Milutinovic