Read e-book online System Specification and Design Languages: Selected PDF

By Sacha Loitz, Markus Wedler, Dominik Stoffel (auth.), Tom J. Kaźmierski, Adam Morawiec (eds.)

ISBN-10: 1461414261

ISBN-13: 9781461414261

ISBN-10: 146141427X

ISBN-13: 9781461414278

This e-book brings jointly a variety of the easiest papers from the 13th version of the discussion board on specification and layout Languages convention (FDL), which was once held in Southampton, united kingdom in September 2010. FDL is a good validated overseas discussion board dedicated to dissemination of study effects, sensible reviews and new principles within the program of specification, layout and verification languages to the layout, modelling and verification of built-in circuits, advanced hardware/software embedded structures, and mixed-technology systems.

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Extra info for System Specification and Design Languages: Selected Contributions from FDL 2010

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Will be executed before others so that we may have a faulty data or control flow within the PDG. A correction would imply reconnecting nodes in the PDG because of correcting the data or control flow. 4 Signal Binding Faults Data transfer between modules is reflected by signal bindings. Each port should be bound to a certain signal. Signal binding faults may occur during the design phase. In the PDG, a correction often can be done by reconnecting data edges. Incorrect/Interchanged Signal Binding Suppose that the designer has specified a wrong data transfer behavior between modules leading to a wrong signal binding at a port or interchanged signals between ports.

Knowing such restrictions is important from two points of view: (1) the results returned by the debugging algorithm may be misleading for those bugs that cannot be handled, (2) a comparison to other debugging algorithms becomes possible. We will also discuss why using a quantitative approach like in [3, 11] is difficult and requires further research before a generalization of the results is possible. The contributions of the presented work are • a methodology for evaluating debugging algorithms, • a fault model on the HDL level to classify design bugs, and • a discussion and evaluation of a quantitative approach to assess debugging algorithms.

1). The respective transition system consists of one state x0 and one transition per offered service and port as depicted in Fig. 7. 5 (Shared Obj. Mapping). Let SO = (S, I, Δ ) be an OSSS Shared Object and p an OSSS port bound to SO. , n}} with t p,i = (prec p , s p,i , x0 → {(psnd p , Δ (si ))}, x0 ) (p I) • P out = {psnd p | p I} 3 Mapping of Concurrent Object-Oriented Models... 47 Fig. 3 Task Model In a function network representation, OSSS tasks are modelled as function nodes while their input and output ports result from the port-interface mapping (see Sect.

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System Specification and Design Languages: Selected Contributions from FDL 2010 by Sacha Loitz, Markus Wedler, Dominik Stoffel (auth.), Tom J. Kaźmierski, Adam Morawiec (eds.)


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