By Ming-Dou Ker
The booklet all semiconductor equipment engineers needs to learn to realize a pragmatic believe for latchup-induced failure to provide lower-cost and higher-density chips.Transient-Induced Latchup in CMOS built-in Circuits equips the training engineer with the entire instruments had to handle this frequent challenge whereas turning into more adept at IC format. Ker and Hsu introduce the phenomenon and uncomplicated actual mechanism of latchup, explaining the serious matters that experience resurfaced for CMOS applied sciences. as soon as readers can achieve an realizing of the traditional practices for TLU, Ker and Hsu speak about the actual mechanism of TLU lower than a system-level ESD attempt, whereas introducing an effective component-level TLU size setup. The authors then current experimental methodologies to extract secure and area-efficient compact structure principles for latchup prevention, together with structure ideas for I/O cells, inner circuits, and among I/O and inner circuits. The booklet concludes with an appendix giving a pragmatic instance of extracting format ideas and directions for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process.Presents actual circumstances and suggestions that ensue in advertisement CMOS IC chipsEquips engineers with the talents to preserve chip format region and reduce time-to-marketWritten by means of specialists with real-world adventure in circuit layout and failure analysisDistilled from a variety of classes taught by means of the authors in IC layout homes worldwideThe in basic terms publication to introduce TLU less than system-level ESD and EFT testsThis publication is vital for training engineers excited by IC layout, IC layout administration, process and alertness layout, reliability, and failure research. Undergraduate and postgraduate scholars, focusing on CMOS circuit layout and format, will locate this e-book to be a necessary creation to real-world difficulties and a key reference through the process their careers.
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The publication all semiconductor equipment engineers needs to learn to realize a realistic believe for latchup-induced failure to supply lower-cost and higher-density chips. Transient-Induced Latchup in CMOS built-in Circuits equips the training engineer with all of the instruments had to tackle this established challenge whereas changing into more adept at IC structure.
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Extra resources for Transient-Induced Latchup in CMOS Integrated Circuits
During the period of 50 ns ≤ t ≤ 75 ns, TLU will not be triggered on by the Nwell/P-substrate junction displacement current. 5V. (Reprinted with permission from IEEE). 15 shows the simulated two-dimensional current flow lines with respect to various transient timing points with a positive VCharge. The N-well/P-substrate junction displacement current will not cause TLU (timing points A and B). However, a large forward well (substrate) contact current will appear when the N-well/P-substrate junction is forward-biased (timing points C and D), and then TLU will certainly be triggered on if ISb is large enough (timing points E–H).
5] Hamdy, E. and Mohsen, A. (1983) Characterization and modeling of transient latchup in CMOS technology, International Electron Devices Meeting Technical Digest, IEEE, New York, NY, USA, pp. 172–175. , Takahashi, H. and Nakamura, T. (1983) Latchup immunity against noise pulses in a CMOS double well structure, International Electron Devices Meeting Technical Digest, IEEE, New York, NY, USA, pp. 168–171. R. P. (1984) Layout and bias considerations for preventing transiently triggered latchup in CMOS.
The IDD current magnitude and waveform are measured by a separated current probe. The current-blocking diode, which is used to prevent the capacitor-discharged current from flowing into the power supply, is used to avoid the possible over-estimation for the TLU immunity of the DUT [1, 2]. The current-limiting resistance is used to avoid the EOS damage to the DUT under a high-current latchup state . 1: Component-level TLU measurement setup with a bipolar trigger [1–3]. This can accurately simulate how a CMOS IC will be disturbed by the ESD-generated noises in the system-level ESD test.
Transient-Induced Latchup in CMOS Integrated Circuits by Ming-Dou Ker